Yield enhancing defect tolerance techniques for FPGAs

is expected to increase. This makes maintaining device yield a challenge. Also, it may be expected that more and more defect circuits will pass the production tests as the device testing challenge grows due to more and more transistors being compacted onto a single chip. Reconfigurable technology has experienced an increasing popularity in recent years. Similar to ASIC design, reconfigurable technology suffers from production defects. However, unlike ASIC design, reconfigurable technology provides a bridge between production and the application designer. The inclusion of defect tolerance in the FPGA architecture could provide a functionally correct FPGA for the application designer, despite production defects. As such, the application designer is relieved of the extra complexity of designing for imperfect devices. This paper presents a survey of known approaches to making defect tolerant FPGAs and discusses their advantages and disadvantages, especially in the context of maintaining FPGA yield and device correctness.

Defect Tolerance Inspired by Artificial Evolution

Defect densities in integrated circuits are expected to in-crease as the semiconductor feature size decreases. Some form of transistor level defect tolerance is, therefore, desir-able to reduce this increasing production challenge. Series and parallel replication of transistors can be applied to a circuit for tolerating stuck-open and stuck-closed transis-tors. The circuit is, however, still damaged by gate/drain and gate/source shorts. This paper applies an evolutionary algorithm to evolve a circuit tolerant to any single short between two transis-tor terminals. The evolved circuit is then analysed and a general defect tolerance technique is formed based on the evolved circuit. Applying the new technique to a cir-cuit results in tolerance to any single stuck-open, stuck-closed, gate/drain shorted or gate/source shorted transis-tor. A Monte Carlo experiment compares the reliability of the new technique applied to a NAND gate with other re-dundant NAND gate implementations.